The realization of integrated circuits is often obtained in the following manner:
One begins with a highly purified block of monocrystalline silicon which is cut into thin slices in order to obtain substrates in the form of discs such as that, P, shown on FIG. 1 and of which the dimensions are intended so that each of them may group together at least several hundreds of elementary circuits which are symbolized on the figure by the small squares C. The circumference of these discs which are often referred to as "wafers", is generally not entirely round and shows two diametrally opposed linear portions of unequal length which are designated by the indications a and b on FIG. 1 which, however, in reality are much less pronounced than on the drawing.
In most cases the substrates are initially submitted to a treatment which enables forming on the surface thereof, i.e. that on which the circuits are to be integrated, a protective layer of silicon dioxide (SiO.sub.2).
The number, type and the order of succession of the operations which follow thereafter depend naturally on the integration technology employed and the nature of the elements which compose each circuit to be integrated. Principally, it involves operations of doping and local depositions of layers which may be conductive, semiconductive or insulating. Most of these operations are preceded by a phase in which the zones to be treated are limited by using a well-known technique of photo-engraving.
Once these various stages have been undertaken one proceeds to the realization of the metallizations which serve to couple different elements of each circuit among one another and/or to placing of the connection studs but which also often serves to terminate the manufacture of certain components, for instance to form the gate of a transistor or of the second plate of a capacitor. In certain cases one may foresee several networks of interconnections superposed on one another which are separated by insulating layers.
The so-called circuits being then terminated such are covered over by an insulating protective layer, for instance a layer of glass.
Next one proceeds to the formation of connection studs as previously mentioned, more commonly known as "bumps", thereafter the circuits are separated from one another by breaking up the silicon substrate into "chips" often after having previously thinned it down.
There then remains nothing more but to fix the chips onto supports, to couple together the connection studs by means of thin wires, e.g. of gold, to the exterior connectors and finally to encapsulate each circuit in a sealed casing or to enrobe it with plastic always allowing the exterior connectors to exit.
Naturally, most of the operations that take place after the enrobing of the circuits by a protective layer are followed by inspection or by testing (optical inspections, electric testing before and after the placing into the casing, tests of the sealing of the casing, etc.).
FIGS. 2a to 2h illustrate by way of example a process which is presently employed to form the connection studs in gold on circuits previously integrated on a silicon substrate, when the metallizations have been obtained in aluminum. The relationships between the thicknesses of the different layers as represented on the figures evidently do not correspond to reality.
The cross-section of FIG. 2a shows the substrate of integrated circuits in a zone where there must be obtained a connection stud. Thereat the substrate 1 is covered over by at least one layer 2 of silicium (SiO.sub.2), a metallization in aluminum 3 and a protective layer 4, for instance of glass.
As is shown by FIG. 2b the first stage of the process consists of opening a window 10 in the protective layer 4, generally of square or rectangular form, at each place where a connection stud is to be formed. This is realized by utilizing the technique of photo-engraving.
Next one deposits by evaporation under vacuum a layer of titanium-tungsten 5, then a layer of gold 6, this over the entire surface of the substrate (see FIG. 2c). These intermediate metallic layers are provided to avoid that the gold to be thereafter galvanically deposited diffuses to the interior of the aluminum forming the metallization. This phase may be unnecessary if the metallizations themselves are of gold.
When the deposition of the intermediate layers 5 and 6 has been effected, the front and back surfaces of the substrate are covered over by a layer of photo-sensitive resin respectively 7 and 8 (see FIG. 2d). Since the layer 8 on the back surface has as its only purpose that of avoiding gold deposition on this surface when the substrate is ulteriorly placed in the galvanic bath, this layer may very well consist of another insulating material, e.g. of a lacquer, which is not attacked by the products forming the bath.
Next the front face of the substrate is exposed to light across a mask and one proceeds to the development operation which enables opening the windows in the layer of resin 7 and thus baring the layer of gold 6. As shown by FIG. 2e these windows are centered on and are visibly larger than windows 10 which have been opened in the protective layer 4.
After having effected by suitable means a careful cleaning of the substrate to remove every trace of the resin on the gold layer 6, at places where the latter has been bared, one proceeds with the realization of the connection studs.
For this one usually begins by placing several substrates side by side on one or several supports which are thereafter plunged into an electrolytic bath containing a solution of one or several gold salts often together with one or several additives and in which is placed at least one anode.
The electrical coupling, which enables placing the gold film 6 and the underlying conductive layers 3, 5 of each substrate at a negative potential thus to cause these layers to play the role of cathode during the time that the substrates are immersed in the bath, is obtained by means of one or several, for instance three, contact points which penetrate the layer of photo-sensitive resin 7 at places where the latter still remains and which are coupled to the negative terminal of the feed voltage source serving to energize the bath. The FIG. 2f shows one of these contact points designated by the indication 12. Naturally to avoid risk of damaging the circuits, the points are arranged at the periphery of the substrate and are not necessarily in proximity to places where the connection studs are to be formed.
In certain cases the contact points are fixed to the substrate supports and are manually placed before the substrates are immersed in the bath, but it may also happen that these points are not coupled to the support. In certain machines for instance they may be fixed to a cover and are only brought into position when the cover is lowered.
When the substrates have remained a sufficient length of time in the bath for the connection studs to have attained the desired thickness, they are removed from the vat and dried.
It then remains to remove the resin 7 still on the front face of the substrates and the protective layer 8 on the back surface (see FIG. 2g), to remove likewise the layers of gold 6 and titanium-tungsten 5 elsewhere than at the locations of the connection studs 11 (see FIG. 2h), to inspect the substrates, to submit these to a thermal treatment to assure a good crystalline coupling between the different metallic layers 3, 5, 6 and 11 and finally to effect an electrical test.
This process of providing connection studs has been chosen as example for a reason which will appear hereinafter but it is evident that there exist others more or less different according to the technology employed to obtain the integrated circuits. For example, the process would no longer be the same as that which has just been described, all else being equal, if the metallizations 3 were not of aluminum but rather gold and/or if the connection studs were realized in another metal, for example copper.
Machines presently available for galvanic treatment of integrated circuit substrates exist in different forms, more or less complicated, but all have a major difficulty, that of enabling the treatment of only a very small number of substrates at a time. For instance there exists at present on the market expensive and sophisticated apparatus which accepts only twenty-four substrates at a time.
From this fact the formation of connection studs is often the cause of a slowing down in the production of integrated circuits, except in the case of substantial investments to provide a sufficiently large number of machines moreover taking up a great deal of space.
This invention has as its purpose, if not to avoid entirely, at least to minimize this difficulty by multiplying the number of substrates which may be treated at the same time in one and the same machine.
On the other hand, the low rate of production at the stage of formation of the connection studs is also due to the fact that these necessitate, as one has seen, a large number of operations.
Another purpose of the invention is to enable to the extent possible, the elimination of one or several of these operations.